Methods for addressing high capacity SDRAM-like memory without increasing pin cost
US10504572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2017 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Nov 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.