Method of adjusting signal to noise ratio of SRAM and invertor structure
US10504788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2019 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Mar 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
Abstract
An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.