Target location in semiconductor manufacturing
US10504802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2017 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Oct 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of overlay control in silicon wafer manufacturing comprises firstly locating a target comprising a diffraction grating on a wafer layer; and then measuring the alignment of patterns in successive layers of the wafer. The location of the target may be done by the pupil camera rather than a vision camera by scanning the target to obtain pupil images at different locations along a first axis. The pupil images may comprise a first order diffraction pattern for each location. A measurement of signal intensity in the first order diffraction pattern is then obtained for each location. The variation of signal intensity with location along each axis is then analyzed to calculate the location of a feature in the target.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.