Semiconductor device and method of manufacturing the same
US10504916B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2015 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Nov 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory device and method of manufacturing the same, an isolation structure is embedded between the common source region and the substrate thereunder, which can inhibit the undesired diffusion of impurities during the implantation of the common source region, avoiding operation failure due to excessive diffusion of impurities. In programming and reading states of the three-dimensional memory device, electrons flow from the common source region to bit line; while in erase states, holes are injected from the substrate. Due to the isolation structure, the three-dimensional memory device achieves spatial separation of electrons from holes required for programming/erasing, improving the erasing efficiency and the integration as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.