Semiconductor structure and manufacturing method of the same
US10504958B2 · kind B2 · utility
4Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Apr 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F10/329
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for manufacturing the semiconductor structure. The method includes forming an Nth metal layer, forming a plurality of magnetic tunneling junctions (MTJs) over the Nth metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, forming a top electrode via concaving upward over each of the plurality of MTJs, and forming an (N+M)th metal layer over the plurality of MTJs. A semiconductor structure manufactured according to present disclosure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.