RRAM memory cell with multiple filaments
US10504963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Feb 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/821
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, the present disclosure relates to a memory circuit having a first resistive random access memory (RRAM) element and a second RRAM element arranged within a dielectric structure over a substrate. The first RRAM element has a first conjunct electrode separated from a first disjunct electrode by a first data storage layer. The second RRAM element has a second conjunct electrode separated from a second disjunct electrode by a second data storage layer. A control device is disposed within the substrate and has first terminal coupled to the first conjunct electrode and the second conjunct electrode and a second terminal coupled to a word-line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.