Method for preparing cap-layer-structured gallium oxide field effect transistor
US10505024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2017 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Nov 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02581
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.