Method of manufacturing a semiconductor device having a gate with ferroelectric layer
US10505040B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Jan 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device comprises forming a first fin and a second fin on a first active region and a second active region of a semiconductor substrate, respectively. A first dummy gate is formed over the first fin and a second dummy gate is formed over the second fin, wherein the first dummy gate has a first gate width along a lengthwise direction of the first fin, the second dummy gate has a second gate width along the lengthwise direction of the second fin, the first gate width is different from the second gate width. At least one of the first dummy gate and the second dummy gate is removed. A ferroelectric layer is then formed over the semiconductor substrate, in which the first dummy gate and/or the second dummy gate is removed. At least one metal gate electrode is formed on the ferroelectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.