Chia-Cheng Ho
48Patents
5h-index
41Co-inventors
65Inventor score
Filing activity: Jul 15, 2010 → Aug 10, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8796759B2 | Fin-like field effect transistor (FinFET) device and method of manufacturing same | Electricity | 222 | Active |
| US8881066B2 | Mandrel modification for achieving single fin fin-like field effect transistor (FinFET) device | Electricity | 20 | Active |
| US8609499B2 | FinFETs and the methods for forming the same | Electricity | 15 | Active |
| US8759184B2 | FinFETs and the methods for forming the same | Electricity | 15 | Active |
| US9029958B2 | FinFETs and the methods for forming the same | Electricity | 6 | Active |
| US10818562B2 | Semiconductor structure and testing method thereof | Electricity | 4 | Active |
| US10707347B2 | Transistor with a negative capacitance and a method of creating the same | Electricity | 3 | Active |
| US11164970B2 | Contact field plate | Electricity | 3 | Active |
| US9601598B2 | Method of manufacturing a fin-like field effect transistor (FinFET) device | Electricity | 3 | Active |
| US10141310B2 | Short channel effect suppression | Electricity | 3 | Active |
| US9379217B2 | FinFETs and the methods for forming the same | Electricity | 3 | Active |
| US10861946B1 | Field plate structure for high voltage device | Electricity | 2 | Active |
| US10872893B2 | Dual nitride stressor for semiconductor device and method of manufacturing | Electricity | 1 | Active |
| US11227828B2 | Semiconductor device and manufacturing method thereof | Electricity | 1 | Active |
| US10732209B2 | Semiconductor test device and manufacturing method thereof | Electricity | 1 | Active |
| US10670641B2 | Semiconductor test device and manufacturing method thereof | Electricity | 1 | Active |
| US10395937B2 | Fin patterning for semiconductor devices | Electricity | 1 | Active |
| US11121225B2 | Field plate structure to enhance transistor breakdown voltage | Electricity | 1 | Active |
| US10505040B2 | Method of manufacturing a semiconductor device having a gate with ferroelectric layer | Electricity | 1 | Active |
| US8906710B2 | Monitor test key of epi profile | Electricity | 1 | Active |
| US11387360B2 | Transistor with a negative capacitance and a method of creating the same | Electricity | 1 | Active |
| US11411086B2 | Field plate and isolation structure for high voltage device | Electricity | 1 | Active |
| US10797174B2 | Semiconductor device with fin end spacer dummy gate and method of manufacturing the same | Electricity | 1 | Active |
| US9728461B2 | Method of forming semiconductor device with different threshold voltages | Electricity | 1 | Active |
| US9768301B2 | Short channel effect suppression | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.