Three-dimensional integration for qubits on multiple height crystalline dielectric
US10505096B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | May 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/6627
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.