Switching layer scheme to enhance RRAM performance
US10505107B2 · kind B2 · utility
4Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Dec 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/883
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a lower electrode over a conductive interconnect, and an upper electrode over the lower electrode. A data storage structure is disposed between the lower electrode and the upper electrode. The data storage structure includes a plurality of metal oxide layers having one or more metals from a first group of metals. A concentration of the one or more metals from the first group of metals changes as a distance from the lower electrode increases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.