Confined phase change memory with double air gap
US10505111B1 · kind B1 · utility
24Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Jul 20, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Jul 20, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for reducing heat loss to adjacent semiconductor structures. The method includes forming a plurality of conductive lines within an interlayer dielectric, forming a barrier layer over at least one conductive line of the plurality of conductive lines, forming a via extending to a top surface of the barrier layer, and defining dual air gaps within the via and over the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.