Inventor · Watervliet, NY, US

Balasubramanian Pranatharthiharan

213Patents
13h-index
113Co-inventors
85Inventor score

Filing activity: May 1, 2006 → Apr 19, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9660028B1 Stacked transistors with different channel widths Electricity 69 Active
US9064801B1 Bi-layer gate cap for self-aligned contact formation Electricity 31 Active
US9337094B1 Method of forming contact useful in replacement metal gate processing and related semiconductor structure Electricity 28 Active
US10505111B1 Confined phase change memory with double air gap Emerging Cross-Sectional Technologies 24 Active
US8753970B2 Methods of forming semiconductor devices with self-aligned contacts and the resulting devices Electricity 21 Active
US8586455B1 Preventing shorting of adjacent devices Electricity 21 Active
US9431399B1 Method for forming merged contact for semiconductor device Electricity 18 Active
US9721848B1 Cutting fins and gates in CMOS devices Electricity 17 Active
US9741823B1 Fin cut during replacement gate formation Electricity 16 Active
US9034741B2 Halo region formation by epitaxial growth Electricity 15 Active
US9570555B1 Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices Electricity 15 Active
US9443853B1 Minimizing shorting between FinFET epitaxial regions Electricity 14 Active
US9397006B1 Co-integration of different fin pitches for logic and analog devices Electricity 14 Active
US9923078B2 Trench silicide contacts with high selectivity process Electricity 13 Active
US9472447B1 Confined eptaxial growth for continued pitch scaling Electricity 13 Active
US9685340B2 Stable contact on one-sided gate tie-down structure Electricity 12 Active
US8937359B2 Contact formation for ultra-scaled devices Electricity 11 Active
US9147576B2 Gate contact with vertical isolation from source-drain Electricity 11 Active
US9305923B1 Low resistance replacement metal gate structure Electricity 10 Active
US9691765B1 Fin type field effect transistors with different pitches and substantially uniform fin reveal Electricity 10 Active
US9935168B2 Gate contact with vertical isolation from source-drain Electricity 8 Active
US9704753B2 Minimizing shorting between FinFET epitaxial regions Electricity 8 Active
US9293551B2 Integrated multiple gate length semiconductor device including self-aligned contacts Electricity 8 Active
US9997418B2 Dual liner silicide Electricity 8 Active
US9461168B1 Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices Electricity 7 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.