Patent · US Active

Simplified bias scheme for digital designs

US10505545B1 · kind B1 · utility

1Cited by

0References

20Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Stefan G. Block · Munich, DE
Jurgen Dirks · Bochum, DE
Herbert Johannes Preuthen · Dorfen, DE
Ulrich Hensel · Radeberg, DE

Key dates

Filing date	Nov 14, 2018
Grant date	Dec 10, 2019
Priority date	—
Expiry date	Nov 14, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D86/01
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Structures for a circuit including field-effect transistors and methods for fabricating and operating such circuits. A plurality of logic cells with a first well and a second well. The first well is directly connected with ground. A tap cell includes an inverter having an output connected with the second well. The inverter is configured to provide a bias voltage having a first state in which a positive voltage is supplied to the second well and a second state in which the second well is connected with ground.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.