Multi-chip structure having configurable network-on-chip
US10505548B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | May 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17768
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips is described herein. In an example, an apparatus includes a first chip comprising a first processing system and a first configurable NoC connected to the first processing system, and includes a second chip comprising a second processing system and a second configurable NoC connected to the second processing system. The first and second configurable NoCs are connected together via an external connector. The first and second processing systems are operable to obtain first and second information from off of the first and second chip and configure the first and second configurable NoCs based on the first and second information, respectively. The first and second processing systems are communicatively coupled with each other via the first and second configurable NoCs when the first and second configurable NoCs are configured based on the first and second information, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.