Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin
US10505705B1 · kind B1 · utility
1Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Dec 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03885
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver is provided that generates a data sampling clock that is offset by clock offset that is a function of a decision feedback equalizer gain to account for a data sampling timing error that would occur without the clock delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.