Minhan Chen
22Patents
5h-index
27Co-inventors
69Inventor score
Filing activity: May 23, 2001 → Nov 3, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6535043B2 | Clock signal selection system, method of generating a clock signal and programmable clock manager including same | Electricity | 35 | Expired |
| US7268624B2 | Differential amplifier offset voltage minimization independently from common mode voltage adjustment | Electricity | 10 | Expired |
| US7486114B2 | Signal detector with calibration circuit arrangement | Electricity | 9 | Active |
| US8798204B2 | Serial link receiver for handling high speed transmissions | Electricity | 8 | Active |
| US9385695B2 | Offset calibration for low power and high performance receiver | Electricity | 5 | Active |
| US9209948B2 | Testing a decision feedback equalizer (‘DFE’) | Electricity | 3 | Active |
| US11159151B1 | Calibrating a phase interpolator by amplifying timing differences | Electricity | 3 | Active |
| US9444657B2 | Dynamically calibrating the offset of a receiver with a decision feedback equalizer (DFE) while performing data transport operations | Electricity | 3 | Active |
| US9014254B2 | Testing a decision feedback equalizer (‘DFE’) | Electricity | 2 | Active |
| US10326417B1 | Offset nulling for high-speed sense amplifier | Electricity | 1 | Active |
| US9614502B2 | Accurate sample latch offset compensation scheme | Electricity | 1 | Active |
| US10965442B2 | Low-power, low-latency time-to-digital-converter-based serial link | Electricity | 1 | Active |
| US10505705B1 | Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin | Electricity | 1 | Active |
| US8183920B2 | Variable gain amplifier with reduced power consumption | Electricity | 0 | Active |
| US9184948B2 | Decision feedback equalizer (‘DFE’) with a plurality of independently-controlled isolated power domains | Electricity | 0 | Active |
| US10079698B1 | Apparatus and method for calibrating a receiver with a decision feedback equalizer (DFE) | Electricity | 0 | Active |
| US11953527B2 | Peak voltage amplitude detectors tolerant to process variation and device mismatch and related methods | Electricity | 0 | Active |
| US9722823B2 | Offset calibration for low power and high performance receiver | Electricity | 0 | Active |
| US12379695B2 | Time-to-digital converters (TDC) employing a single-stage delay pair and noise shaping for wide input range and reduced quantization noise in a phase-locked loop (PLL) | Electricity | 0 | Active |
| US12212327B2 | Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods | Electricity | 0 | Active |
| US12362902B2 | Phase interpolator (PI) with clamping circuit to limit operation to range having optimal integral non-linearity and related methods | Electricity | 0 | Active |
| US12216434B2 | Time to digital converter (TDC) circuit with self-adaptive time granularity and related methods | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.