Support for improved throughput in a memory device
US10509589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2015 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | May 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of controlling a memory device can include: (i) receiving a first read command for a critical byte, where the critical byte resides in a first group of a memory array on the memory device; (ii) reading the critical byte from the memory array in response to the first read command, and providing the critical byte; (iii) reading a next byte in the first group; (iv) outputting the next byte from the first group when a clock pulse; (v) repeating the reading the next byte and the outputting the next byte for each byte in the first group; (vi) reading a first byte in a second group of the memory array, where the second group is sequential to the first group, and where each group is allocated to a cache line; and (vii) outputting the first byte from the second group when a clock pulse is received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.