Method for layout generation with constrained hypergraph partitioning
US10509883B2 · kind B2 · utility
3Cited by
17References
20Claims
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Key dates
| Filing date | Jan 24, 2017 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Mar 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.