Write scheme for a static random access memory (SRAM)
US10510385B2 · kind B2 · utility
1Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2018 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Feb 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure includes a write driver circuit configured to drive both a true bitline side and a complement bitline side up to a power supply and down to ground such that one of the true bitline side and the complement bitline side is driven to ground and another of the true bitline side and the complement bitline side is driven to a high level at a same time and before a precharge below a level of the power supply of the one of the true bitline side and the complement bitline side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.