Inventor · Milpitas, CA, US

Wei Zhao

67Patents
13h-index
94Co-inventors
83Inventor score

Filing activity: Aug 18, 2011 → Nov 30, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9530790B1 Three-dimensional memory device containing CMOS devices over memory stack structures Electricity 108 Active
US9502471B1 Multi tier three-dimensional memory devices including vertically shared bit lines Electricity 83 Active
US9177966B1 Three dimensional NAND devices with air gap or low-k core Electricity 58 Active
US9286994B1 Method of reducing hot electron injection type of read disturb in dummy memory cells Physics 38 Active
US9361993B1 Method of reducing hot electron injection type of read disturb in memory Physics 35 Active
US9236396B1 Three dimensional NAND device and method of making thereof Electricity 30 Active
US9640273B1 Mitigating hot electron program disturb Physics 29 Active
US9305849B1 Method of making a three dimensional NAND device Electricity 27 Active
US9761320B1 Reducing hot electron injection type of read disturb during read recovery phase in 3D memory Physics 25 Active
US9530785B1 Three-dimensional memory devices having a single layer channel and methods of making thereof Electricity 15 Active
US9406391B1 Method of reducing hot electron injection type of read disturb in dummy memory cells Physics 14 Active
US9236131B1 Bias to detect and prevent short circuits in three-dimensional memory device Electricity 14 Active
US10685978B1 Three-dimensional memory device with drain-select-level isolation structures and method of making the same Electricity 13 Active
US10636500B1 Reducing read disturb in two-tier memory device by modifying ramp up rate of word line voltages during channel discharge Electricity 12 Active
US10770157B1 Method of reducing injection type of program disturb during program pre-charge in memory device Physics 11 Active
US9515079B2 Three dimensional memory device with blocking dielectric having enhanced protection against fluorine attack Electricity 10 Active
US9230982B1 Protective structure to prevent short circuits in a three-dimensional memory device Electricity 10 Active
US10629272B1 Two-stage ramp up of word line voltages in memory device to suppress read disturb Physics 10 Active
US9378832B1 Method to recover cycling damage and improve long term data retention Physics 10 Active
US9336891B2 Look ahead read method for non-volatile memory Physics 9 Active
US10685979B1 Three-dimensional memory device with drain-select-level isolation structures and method of making the same Electricity 9 Active
US10790003B1 Maintaining channel pre-charge in program operation Physics 7 Active
US10685723B1 Reducing read disturb in two-tier memory device by modifying duration of channel discharge based on selected word line Electricity 6 Active
US11101288B2 Three-dimensional memory device containing plural work function word lines and methods of forming the same Electricity 4 Active
US11063063B2 Three-dimensional memory device containing plural work function word lines and methods of forming the same Electricity 4 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.