Memory read stability enhancement with short segmented bit line architecture
US10510403B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2018 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Dec 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.