Memory device using comb-like routing structure for reduced metal line loading
US10510415B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2018 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Oct 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/80896
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and one or more peripheral devices on the first substrate. The second semiconductor structure includes a first set of conductive lines electrically coupled with a first set of a plurality of vertical structures and a second set of conductive lines electrically coupled with a second set of the plurality of vertical structures different from the first set of the plurality of vertical structures. The first set of conductive lines are vertically distanced from one end of the plurality of vertical structures and the second set of conductive lines are vertically distanced from an opposite end of the plurality of vertical structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.