Memory devices with read level calibration

US10510422B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Gary F. Besinga · Boise, US
• Peng Fei · Shanghai, CN
• Michael G. Miller · Boise, US
• Roland J. Awusie · Boise, US
• Kishore Kumar Muchherla · Fremont, US
• Renato C. Padilla · Folsom, US
• Harish Reddy Singidi · Fremont, US
• Jung Sheng Hoei · Merced, US
• Gianni Stephen Alsasua · Rancho Cordova, US

Key dates

• Filing date: Sep 10, 2018
• Grant date: Dec 17, 2019
• Expiry date: Sep 10, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2207/2254
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.