Mitigating disturbances of memory cells
US10510423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2017 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Aug 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.