Methods of producing self-aligned vias
US10510602B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2018 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Aug 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1026
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus to form fully self-aligned vias are described. A first metal film is formed in the recessed first conductive lines and on the first insulating layer of a substrate comprising alternating conductive lines and a first insulating layer. Pillars and a sheet are formed from the first metal film. Some of the pillars and a portion of the sheet are selectively removed and a second insulating layer is deposited around the remaining pillars and sheet. The remaining pillars and sheet are removed to form vias and a trench in the second insulating layer. A third insulating layer is deposited in the vias and trench and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is selectively etched from some of the filled vias to form via openings to the first conductive line and a trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.