Inventor · San Jose, CA, US

He Ren

64Patents
8h-index
121Co-inventors
77Inventor score

Filing activity: Mar 15, 2013 → Feb 10, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8969212B2 Dry-etch selectivity Electricity 182 Active
US9384997B2 Dry-etch selectivity Electricity 145 Active
US9576810B2 Process for etching metal using a combination of plasma and solid state sources Electricity 36 Active
US9761489B2 Self-aligned interconnects formed using substractive techniques Electricity 18 Active
US10957533B2 Methods for etching a structure for semiconductor applications Electricity 14 Active
US10636704B2 Seam-healing method upon supra-atmospheric process in diffusion promoting ambient Electricity 13 Active
US10916433B2 Methods of forming metal silicide layers and metal silicide layers formed therefrom Electricity 13 Active
US10049927B2 Seam-healing method upon supra-atmospheric process in diffusion promoting ambient Electricity 13 Active
US9646876B2 Aluminum nitride barrier layer Electricity 8 Active
US9269563B2 Methods for forming interconnect structure utilizing selective protection process for hardmask removal process Electricity 6 Active
US10256144B2 Process integration approach of selective tungsten via fill Electricity 4 Active
US9299605B2 Methods for forming passivation protection for an interconnection structure Electricity 4 Active
US9640424B2 Integrated metal spacer and air gap interconnect Electricity 4 Active
US9508561B2 Methods for forming interconnection structures in an integrated cluster system for semicondcutor applications Electricity 4 Active
US9305831B2 Integrated metal spacer and air gap interconnect Electricity 4 Active
US10643895B2 Self-aligned interconnects formed using subtractive techniques Electricity 3 Active
US10388533B2 Process integration method to tune resistivity of nickel silicide Electricity 2 Active
US9601431B2 Dielectric/metal barrier integration to prevent copper diffusion Electricity 2 Active
US10109520B2 Methods for depositing dielectric barrier layers and aluminum containing etch stop layers Electricity 2 Active
US10692759B2 Methods for manufacturing an interconnect structure for semiconductor devices Electricity 2 Active
US10685849B1 Damage free metal conductor formation Electricity 1 Active
US10790191B2 Selective removal process to create high aspect ratio fully self-aligned via Electricity 1 Active
US9299577B2 Methods for etching a dielectric barrier layer in a dual damascene structure Electricity 1 Active
US11164780B2 Process integration approach for selective metal via fill Electricity 1 Active
US10008448B2 Dielectric/metal barrier integration to prevent copper diffusion Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.