Methods for threshold voltage tuning and structures formed thereby
US10510621B2 · kind B2 · utility
4Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Apr 13, 2018 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Apr 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.