Planarizing RDLs in RDL-first processes through CMP process
US10510645B2 · kind B2 · utility
5Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2018 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Apr 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a buffer dielectric layer over a carrier, and forming a first dielectric layer and a first redistribution line over the buffer dielectric layer. The first redistribution line is in the first dielectric layer. The method further includes performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer, forming a metal post over and electrically coupling to the first redistribution line, and encapsulating the metal post in an encapsulating material. The encapsulating material contacts a top surface of the planarized top surface of the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.