Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
US10510650B2 · kind B2 · utility
54Cited by
12References
20Claims
0Family size
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Key dates
| Filing date | Jul 2, 2018 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Jul 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1434
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method of manufacture are presented in which a first semiconductor device and second semiconductor device are bonded to a first wafer and then singulated to form a first package and a second package. The first package and second package are then encapsulated with through interposer vias, and a redistribution structure is formed over the encapsulant. A separate package is bonded to the through interposer vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.