Molded chip combination
US10510721B2 · kind B2 · utility
17Cited by
32References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2017 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Aug 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.