Buffer layer(s) on a stacked structure having a via
US10510723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2017 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Oct 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06548
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.