Hitless switching when generating an output clock derived from multiple redundant input clocks

US10514720B1 · kind B1 · utility

Assignee

• Aura Semiconductor Pvt. Ltd · IN

Inventors

• Raja Prabhu J · Kanchinakote, IN
• Ankit Seedher · Kanchinakote, IN
• Augusto Marques · Austin, US
• Srinath Sridharan · Nagamangala, IN
• Kulbhushan Thakur · Bengaluru, IN

Key dates

• Filing date: May 22, 2019
• Grant date: Dec 24, 2019
• Expiry date: May 22, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/1976
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A phase locked loop (PLL) includes a multiplexer (MUX), a phase detector, a filter block, an oscillator, a frequency divider, and a clock switch controller, and achieves hitless switching between a primary clock and a redundant clock. The clock switch controller, upon detecting a condition requiring switching from the primary clock to the redundant clock, is operable to restart the feedback divider synchronously with respect to the redundant clock, and derive the output of the PLL from the redundant clock. The PLL further includes a delay block to process delayed phase error signals generated by the phase detector. The PLL performs hitless clock switching in the event of input clock loss or in response to a command to switch input clocks. The PLL further includes circuitry for estimating and cancelling residual phase errors.