Ankit Seedher
17Patents
5h-index
26Co-inventors
62Inventor score
Filing activity: May 3, 2005 → Jan 10, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7551114B2 | Reducing power consumption in the early stages of a pipeline sub-ADC used in a time-interleaved ADC | Electricity | 21 | Active |
| US9172303B2 | Power management unit systems and methods | Electricity | 7 | Active |
| US7230473B2 | Precise and process-invariant bandgap reference circuit and method | Physics | 7 | Expired |
| US7724042B2 | Reducing power consumption in an amplification stage driving a sample and hold circuit while maintaining linearity | Physics | 5 | Active |
| US10514720B1 | Hitless switching when generating an output clock derived from multiple redundant input clocks | Electricity | 5 | Active |
| US11588489B1 | Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock | Electricity | 2 | Active |
| US9025791B2 | Pop-up noise reduction in a device | Electricity | 1 | Active |
| US7777655B2 | Wideband switched current source | Electricity | 1 | Active |
| US8841950B2 | Pulse width modulation for switching amplifier | Electricity | 1 | Active |
| US8912798B2 | Circuit for controlling current to light-emitting diode (LED) | Physics | 1 | Active |
| US9742414B2 | Reducing errors due to non-linearities caused by a phase frequency detector of a phase locked loop | Electricity | 0 | Active |
| US12026028B2 | Preventing reverse-current flow when an integrated circuit operates using power supplies of different magnitudes | Electricity | 0 | Active |
| US12149255B2 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Electricity | 0 | Active |
| US11923864B2 | Fast switching of output frequency of a phase locked loop (PLL) | Electricity | 0 | Active |
| US10892765B1 | Relocking a phase locked loop upon cycle slips between input and feedback clocks | Electricity | 0 | Active |
| US12261609B1 | Inter-PLL communication in a multi-PLL environment | Electricity | 0 | Active |
| US11967965B2 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.