Non-uniform memory access (NUMA) mechanism for accessing memory with cache coherence
US10515014B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2017 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Jun 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a data processing system includes a plurality of processors, each of the processors being coupled to each of remaining processors via a processor interconnect, a plurality of memory controllers, each memory controller corresponding to one of the processors, a plurality of memory targets, each memory target includes one or more branches and a plurality of memory leaves for storing data, and an Ethernet switch fabric coupled to the memory controllers and the memory targets. When a first of the memory controllers writes data to a first of the memory leaves, the first memory controller sends a cache coherence message to remaining ones of the memory controllers to indicate that the data stored in the first memory leaf has been updated, such that any of the remaining memory controllers can update its cache by fetching the data from the first memory leaf.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.