Techniques for forming low stress mask using implantation

US10515802B2 · kind B2 · utility

Assignee

• Varian Semiconductor Equipment Associates, Inc. · US

Inventors

• Rajesh Prasad · Lexington, US
• Tzu-Yu Liu · San Jose, US
• Edwin Arevalo · Haverhill, US
• Deven Raj Mittal · Middleton, US
• Somchintana Norasetthekul · College Station, US
• Kyuha Shim · Andover, US
• Lauren Liaw · Gloucester, US
• Takaski Shimizu · Gloucester, US
• Nobuyuki Sasaki · Santa Clara, US
• Ryuichi Muira · Gloucester, US
• Hiro Ito · Gloucester, US

Key dates

• Filing date: Jul 9, 2018
• Grant date: Dec 24, 2019
• Expiry date: Jul 9, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31155
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method may include depositing a mask layer on a substrate using physical vapor deposition, wherein an absolute value of a stress in the mask layer has a first value; and directing a dose of ions into the mask layer, wherein the absolute value of the stress in the mask layer has a second value, less than the first value, after the directing the dose.