Patent · US Active

Method for manufacturing semiconductor devices

US10515857B2 · kind B2 · utility

3Cited by

0References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Ling-Yen Yeh · Hsinchu, TW
Carlos H. Diaz · Baoshan, TW
Wilman Tsai · Saratoga, US

Key dates

Filing date	Jan 30, 2018
Grant date	Dec 24, 2019
Priority date	—
Expiry date	Jan 30, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/62
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In a method of manufacturing a circuit including a MOSFET disposed in a MOSFET region and a negative capacitance FET (NCFET) disposed in a NCFET region, a dielectric layer is formed over a channel layer in the MOSFET region and the NCFET region. A first metallic layer is formed over the dielectric layer in the MOSFET region and the NCFET region. After the first metallic layer is formed, an annealing operation is performed only in the NCFET region. After the annealing operation, the first metallic layer is removed from the MOSFET region and the NCFET region. The annealing operation includes irradiating the first metallic layer and the dielectric layer in the NCFET region with an energy beam.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.