Interconnect structure for semiconductor device and methods of fabrication thereof
US10515896B2 · kind B2 · utility
3Cited by
27References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.