Enhanced channel strain to reduce contact resistance in NMOS FET devices
US10515966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2018 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Aug 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.