Semiconductor devices having reduced noise
US10515990B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2018 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Dec 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and methods of forming semiconductor devices are disclosed. In some embodiments, a first trench and a second trench are formed in a substrate, and dopants of a first conductivity type are implanted along sidewalls and a bottom of the first trench and the second trench. The first and second trenches are filled with an insulating material, and a gate dielectric and a gate electrode over the substrate, the gate dielectric and the gate electrode extending over the first trench and the second trench. Source/drain regions are formed in the substrate on opposing sides of the gate dielectric and the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.