Method for manufacturing a semiconductor device
US10516022B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2018 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Jun 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wide bandgap semiconductor device is comprising an (n−) doped drift layer between a first main side and a second main side. On the first main side, n doped source regions are arranged which are laterally surrounded by p doped channel layers having a channel layer depth. P+ doped well layers having a well layer depth, which is at least as large as the channel layer depth is arranged at the bottom of the source regions. A p++ doped plug extends from a depth, which is at least as deep as the source layer depth and less deep than the well layer depth, to a plug depth, which is as least as deep as the well layer depth, and having a higher doping concentration than the well layers, is arranged between the source regions and well layers. On the first main side, an ohmic contact contacts as a first main electrode the source regions, the well layers and the plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.