Method of forming the gate electrode of field effect transistor
US10516031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Oct 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device includes depositing a contact etch stop layer (CESL) over a dummy gate electrode, a source/drain (S/D) region and an isolation feature. The method further includes performing a first CMP to expose the dummy gate electrode. The method further includes removing an upper portion of the CESL. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the dummy gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.