III group nitride semiconductor device and manufacturing method thereof
US10516042B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 15, 2016 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Apr 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An III group nitride semiconductor device comprises: a substrate; a nitride semiconductor layer located on the substrate; a passivation layer located on the nitride semiconductor layer, a portion of the passivation layer in a gate region being etched to expose the nitride semiconductor layer so as to form a gate groove; a composite dielectric layer located on the passivation layer and the gate groove, the composite dielectric layer comprising one or more combination structures of two or more of a nitride dielectric layer, an oxynitride dielectric layer and an oxide dielectric layer which are formed sequentially in the direction away from the substrate; and a source electrode and a drain electrode respectively located in a source region and a drain region on the nitride semiconductor layer, and a gate electrode located in a gate region between the source region and the drain region on the composite dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.