Interface substrate and method of making the same
US10516092B2 · kind B2 · utility
0Cited by
5References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 2, 2016 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Sep 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.