Multiple spacer assisted physical etching of sub 60nm MRAM devices

US10516102B1 · kind B1 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Yi Yang · Zhejiang, CN
• Dongna Shen · San Jose, US
• Yu-Jen Wang · San Jose, US

Key dates

• Filing date: Oct 16, 2018
• Grant date: Dec 24, 2019
• Expiry date: Oct 16, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/85

Abstract

A MTJ stack is deposited on a bottom electrode. A top electrode layer and hard mask are deposited on the MTJ stack. The top electrode layer not covered by the hard mask is etched. Thereafter, a first spacer layer is deposited over the patterned top electrode layer and the hard mask. The first spacer layer is etched away on horizontal surfaces leaving first spacers on sidewalls of the patterned top electrode layer. The free layer not covered by the hard mask and first spacers is etched. Thereafter, the steps of depositing a subsequent spacer layer over patterned previous layers, etching away the subsequent spacer layer on horizontal surfaces leaving subsequent spacers on sidewalls of the patterned previous layers, and thereafter etching a next layer not covered by the hard mask and subsequent spacers are repeated until all layers of the MTJ stack have been etched to complete the MTJ structure.