Computational memory cell and processing array device using memory cells
US10521229B2 · kind B2 · utility
23Cited by
194References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2017 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Sep 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.