Memristor based multithreading
US10521237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2014 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Jun 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.