Data-dependent delay circuits
US10521530B2 · kind B2 · utility
2Cited by
9References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2017 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Oct 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing a logic circuit with data-dependent delays is performed using an electronic design automation system. The logic circuit includes logic paths from logic inputs to at least one logic output. The method includes:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.