Methods and apparatuses to reduce power dissipation in a static random access memory (SRAM) device
US10522218B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Nov 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments herein provide a method for reducing power dissipation in a Static Random Access Memory (SRAM) device. The method includes determining, by the tracking circuit, whether at least one SRAM Bit-Cell discharges power from at least one BL exceeding a pre-defined voltage level required for a sense amplifier to perform a read operation. Furthermore, the method includes reducing, by the WL driver, the power discharged from the at least one BL by controlling a WL voltage power supply switch of the WL driver using a SAE signal and adjusting a pulse width of the at least one WL to pull down the at least one WL using a NMOS circuit when the at least one SRAM Bit-Cell discharges the power from the at least one BL exceeding the pre-defined voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.