Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects and structures resulting therefrom
US10522402B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 2015 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Dec 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate, the dielectric lines raised above the metal lines. A hardmask layer is formed on the metal lines of the lower metallization layer, between and co-planar with the dielectric lines of the lower metallization layer. A grating structure is formed above and orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. A mask is formed above the grating structure. Select regions of the hardmask layer are removed to expose select regions of the metal lines of the lower metallization layer. Metal vias are formed on the select regions of the metal lines of the lower metallization layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.